1. Field
Exemplary embodiments of the present invention relate to a filtering circuit, a phase identity determination circuit and a delay locked loop.
2. Description of the Related Art
A circuit device such as a DDR SDRAM (double data rate synchronous DRAM) performs transmission of various signals and data using an internal clock synchronized with an external clock which is used in an external system. Though a clock inputted to the circuit device is applied initially in a state that it is synchronized with the external clock, it is delayed while passing through various component elements in the device and is not in synchronization with the external clock when it is outputted to an outside of the device. Thus, in order for stable transmission of signals and data, it is to compensate the internal clock for a time taken to load data on a bus in the circuit device such that the outputted internal clock and the external clock are precisely synchronized with each other in the external system. In order to play this role, a delay locked loop is used.
FIG. 1 is a configuration diagram of a conventional delay locked loop.
Referring to FIG. 1, a delay locked loop includes a delay unit 110, a replica delay unit 120, a phase comparison unit 130, a filter unit 140, a lock signal generation unit 150, and a delay value control unit 160.
Operations of the delay locked loop will be described with reference to FIG. 1.
The delay unit 110 delays an input clock ICLK and generates an output clock OCLK. The replica delay unit 120 delays the output clock OCLK by a modeled delay value and generates a feedback clock FBCLK. The phase comparison unit 130 compares the phases of the input clock ICLK and the feedback clock FBCLK. In order to remove noise included in a comparison result PHA of the phase comparison unit 130, the filter unit 140 filters the comparison result PHA of the phase comparison unit 130 and generates a filtered signal FIL. The delay value control unit 160 controls the delay value of the delay unit 110 in response to the filtered signal FIL. The lock signal generation unit 150 activates a lock signal LOCK in response to the filtered signal FIL when the phases of the input clock ICLK and the feedback clock FBCLK become the same with each other. If the lock signal LOCK is activated, the delay value control unit 160 maintains the delay value of the delay unit 110 as the delay value at a time when the lock signal LOCK is activated.
For example, the lock signal generation unit 150 may activate the lock signal LOCK when the phase difference between the input clock ICLK and the feedback clock FBCLK is smaller than a given value. The given value may be a minimum value delayed by the delay unit 110 (hereinafter, referred to as a unit delay value).
The phase comparison unit 130 generates the comparison result PHA of a low level when the phase of the feedback clock FBCLK is earlier than the phase of the input clock ICLK and generates the comparison result PHA of a high level when the phase of the feedback clock FBCLK is later than the phase of the input clock ICLK.
The filter unit 140 samples the output PHA (hereinafter, referred to as the comparison result PHA) of the phase comparison unit 130 in response to an operating clock CLKA. If the number of times the comparison result PHA of the high level is sampled is equal to or greater than a filter depth, the filtered signal FIL of a high level is generated, and if the number of times the comparison result PHA of the low level is sampled is equal to or greater than the filter depth, the filtered signal FIL of a low level is generated. Hereinbelow, explanations will be made for the case that the filter unit 140 updates the logic value of the filtered signal FIL when the comparison result PHA of the same logic value is consecutively sampled by the filter depth. For example, when the filter depth is 5, the filter unit 140 updates the logic value of the filtered signal FIL to the low level when the comparison result PHA of the low level is consecutively sampled 5 times and updates the logic value of the filtered signal FIL to the high level when the comparison result PHA of the high level is consecutively sampled 5 times.
The lock signal generation unit 150 activates the lock signal LOCK when the filtered signal FIL transitions from the low level to the high level. This is because the transition of the filtered signal FIL from the low level to the high level means that the phase difference between the input clock ICLK and the feedback clock FBCLK is smaller than the unit delay value of the delay unit 110.
The delay value control unit 160 increases the delay value of the delay unit 110 when the filtered signal FIL has the low level and decreases the delay value of the delay unit 110 when the filtered signal FIL has the high level. If the lock signal LOCK is activated, the delay value control unit 160 causes the delay unit 110 to maintain a corresponding delay value.
FIG. 2 is a waveform diagram illustrating the features of the conventional delay locked loop.
A half locking phenomenon that the falling edge of the input clock ICLK and the rising edge of the feedback clock FBCLK are locked together due to noise will be described below with reference to FIG. 2.
Due to noise induced by a power drop, etc., the rising edge of the feedback clock FBCLK located at a first position 201 may be moved to a second position 202 while the delay locked loop operates to match the phase of the input clock ICLK and the feedback clock FBCLK. The phase comparison unit 130 generates the comparison result PHA of the low level, and the logic value of the filtered signal FIL is updated to the low level when the comparison result PHA of the low level is consecutively sampled 5 times. The delay value control unit 160 increases the delay value of the delay unit 110 in response to the filtered signal FIL of the low level, by which the rising edge of the feedback clock FBCLK is moved/delayed to a third position 203. Thereafter, if noise is removed, the rising edge of the feedback clock FBCLK is moved to a fourth position 204, and the comparison result PHA of the high level is generated by the phase comparison unit 130. If the comparison result PHA of the high level is consecutively sampled 5 times, the filter unit 140 updates the logic value of the filtered signal FIL to the high level. Since the filtered signal FIL is changed from the low level to the high level, the lock signal generation unit 150 activates the lock signal LOCK. Therefore, the phase of the feedback clock FBCLK is locked at a wrong position.
Such half locking may occur when a period in which noise is generated is longer than the length of filter depth and shorter than two times the length of the filter depth. The length of the filter depth corresponds to the maximum value of the duration of noise which the filter unit 140 may filter. If noise is generated for a shorter period than the length of the filter depth, the filter unit 140 may filter the noise, and if noise is generated is for a longer period than two times the length of the filter depth, the delay value of the delay unit 110 is increased by the delay value control unit 160 and the feedback clock FBCLK goes out of a period in which the half locking may occur. The length of the filter depth is determined by the sampling frequence of the filter unit 140. As the sampling frequence is high, the length of the filter depth is shortened, and as the sampling frequence is low, the length of the filter depth is lengthened. As the length of the filter depth becomes long, the probability of the half locking to occur increases.